The present invention relates silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuits with controllable hysteresis and a method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications.
High performance deep sub-micrometer SOI designs are vulnerable to increased noises from line-to-line capacitance coupling as a result of technology scaling. To restore signal integrity, judicious use of Schmitt trigger receivers can serve as a convenient and transparent solution. The Schmitt trigger is often used to turn a signal with a very slow or sloppy transition into a signal with a sharp transition.
Referring to FIGS. 1, 2A and 2B, in FIG. 1, an unmodified inverting Schmitt trigger circuit is shown. FIGS. 2A and 2B illustrate quasi-static transfer characteristics of an unmodified SOI CMOS Schmitt trigger circuit with all the FET bodies left floating. FIGS. 2A and 2B illustrate transfer curves that are generated under slow input signal slews and long cycle time. The first 500 simulation cycles are shown when the circuit is activated from dormancy. Due to the history effect associated with floating body voltages of the 6 component field effect transistors (FETs) in the unmodified inverting Schmitt trigger circuit, the switching trip points V+ and Vxe2x88x92 suffer a wide degree of uncertainty. In turn, it makes xcex94V=V+xe2x88x92Vxe2x88x92 vary, depending on exact FET body potentials, from one quasi-static sweep to another even when the input voltage scans at a consistently low frequency, mimicking the DC transfer curve. Examples are shown in FIGS. 2A and 2B, where low-frequency input signals, namely 2.5 MHz squared sine waves, are applied to construct the transfer characteristics for the first 500 hundred cycles after a prolonged circuit dormancy. For a bulk CMOS circuit, the low-frequency sweep and its corresponding transfer curve, represent the quasi-static behavior. However, for a floating-body PD/SOI CMOS circuit, due to the dependence of body voltages on the initial condition and operating history of the circuit, the so-called quasi-static transfer characteristics will not be unique and jitters or variations will be present. Thus, the low-frequency sweep unambiguously captures any floating-body-induced hysteresis in the PD/SOI design.
In FIG. 2A, the xcex94V varies from about 310 mV to 420 mV. The example of FIG. 2A is not the worst case in PD/SOI. In particular, a wide 80 mV uncertainty for the V+ edge is observed, which is caused primarily by the gradual threshold voltage drift of NFET N3. Depending on the initial conditions and device sizes, the eye of the transfer curve grows larger or smaller as the cycle proceeds without a controllable or predictable trend. This is exemplified by the marked difference between FIGS. 2A and 2B. In FIG. 2B, the input sweep sequence is reversed from that of FIG. 2A to create a different set of initial conditions for body voltages. Faster sweep, varying duty cycles, extreme fabrication and operating conditions can create more V+, Vxe2x88x92, and xcex94V variation even to the extent that the circuit is no longer able to function within the allowable noise margin specificiation.
A need exists for SOI CMOS Schmitt trigger circuits with controllable hysteresis and a method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications.
A principal object of the present invention is to provide a SOI CMOS Schmitt trigger circuit with controllable hysteresis and a method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications. Other important objects of the present invention are to provide such SOI CMOS Schmitt trigger circuit with controllable hysteresis and method substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis and a method are provided for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications. A SOI CMOS Schmitt trigger circuit with controllable hysteresis includes a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground. An input is applied to a gate of each of the stack of the plurality of field effect transistors (FETs). The stack of the plurality of field effect transistors (FETs) provides an output at a junction of a predetermined pair of the plurality of field effect transistors (FETs). At least one feedback field effect transistor (FET) has a source coupled a junction of a predefined pair of the stack of field effect transistors (FETs) and has a gate coupled to the output. A FET body of each of the stack of the plurality of field effect transistors (FETs) is connected to a voltage supply rail.
In accordance with features of the invention, the stack of the plurality of field effect transistors (FETs) includes a plurality of P-channel field effect transistors (PFETs) and a plurality of N-channel field effect transistors (NFETs). The FET body of each of the plurality of P-channel field effect transistors (PFETs) is connected to a positive voltage supply rail and the FET body of each of the plurality of N-channel field effect transistors (NFETs) is connected to a voltage supply ground rail. The FET body of a P-channel feedback field effect transistor (PFET) is connected to one of a positive voltage supply rail, the gate or the source of the feedback PFET. The FET body of a N-channel feedback field effect transistor (NFET) is connected to one of a voltage supply ground rail, the gate or the source of the feedback NFET. A successive switching threshold adjustment technique is provided. Additional successive switching threshold adjustment is achieved by successive tapping of NFET or PFET feedback devices for the V+ or the Vxe2x88x92 trigger edges, respectively. With this arrangement, higher V+ and lower Vxe2x88x92 are realized without using excessively wide NFET or PFET feedback devices.